1. Field of the Invention
The present invention relates to an offset chip-stacked package structure, and more particularly, to an offset chip-stacked packaging with heat sink structure.
2. Description of the Prior Art
In semiconductor post-processing, many efforts have been made for increasing the scale of the integrated circuits such as memories while minimizing the occupied area. Accordingly, the development of three-dimensional (3D) packaging technology is in progress and the idea of making up a chip-stacked structure has been disclosed.
The prior art has taught that a chip-stacked structure can be formed by firstly stacking a plurality of chips and then electrically connecting the chips to the substrate in a wire bonding process. FIG. 1 is a cross-sectional view of a prior chip-stacked package structure for chips of same or similar sizes. As shown in FIG. 1A, the prior chip-stacked package structures 10 and 100 comprise a package substrate 110, chip 120a, chip 120b, a spacer 130, a plurality of wires 140, and an encapsulant 150. The package substrate 110 is provided with a plurality of pads 112. The chips 120a and 120b are respectively provided with peripherally arranged pads 122a and 122b. The chip 120a is provided on the package substrate 110 while the chip 120b is provided on the chip 120a with a spacer 130 intervened there-between. The chip 120a is electrically connected to the substrate 110 by bonding two ends of one of the wires 140 to the pads 112 and 122a respectively. The chip 120b is electrically connected to the substrate 110 in similar manner. The encapsulant 150 is then provided on the substrate 110 to cover the chips 120a and 120b and the wires 140.